期刊论文

Li, L.

中文

重庆大学学报

1000-582X

2014

37

6

56-64

10.11835/j.issn.1000-582X.2014.06.009

61133005:国家自然科学基金 11B018:湖南省教育厅青年项目 897203005:湖南省博士后基金 12CXYZ01:衡阳师范学院产学研基金

本校为第一且通讯机构

AES密码算法是目前广泛使用的一种加密算法。为了对AES算法进行优化,通过对密钥扩展模块重复调用,实现代码的高效利用。具体方法为在AES算法进行加解密运算时,其中所需的密钥可在其他模块执行时重复调用,即一次生成十轮密钥,通过控制模块实现轮密钥加运算。详细叙述了改进后AES算法的Verilog HDL硬件语言实现,特别是对具体实现过程中关键核心代码进行了清晰描述,经modelsim6.1f仿真验证正确后进行了FPGA硬件实现,对FPGA硬件实现进行了实验结果正确性验证。实验结果表明,优化后的AES算法在Xilinx Virtex-V FPGA上仅占用了3 531个Slice,5 522个LUT,与同类加密算法实现所需的资源数对比,在性能同等...

AES algorithm is a widely used cryptographic algorithm. To improve AES algorithm, it's proposed to repeatedly call key expansion module to realize efficient use of the code. Ten-round keys are generated at the same time, and operations of add round key are achieved by the control module. The key is called repeatedly when the AES algorithm is running for encryption and decryption. The realization of AES is verified by modelsim6. 1f. AES algorithm is designed with Verilog HDL, and a clear description about the critical core code realization of the process is proposed. The hardware implementation...