The power attack of the hardware circuit is going through the steps of algorithm writen in FPGA, power consumption, data processing and analysis. In order to solve the problem of the existing power attack experimental platform because the processing steps are too scattered, feature complex operations and other issues, we've thus developed a higher degree of integration of the experimental platform. The advanced encryption standard (AES) algorithm is taken as an example to illustrate the whole process of implementing the correlation power analys...